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AMD (formerly Xilinx) FPGAs: Part 2 Synthesis and testing on device

Introduction

In the previous tutorial, you ran through the automated simulation of a full adder. In this section you will learn how to synthesis the full adder and run tests on the FPGA device using the Integrated Logic Analyzer (ILA) IP core.

You can find the source code for this example here.

Creating a hardware testbench

Creating a block diagram

The testbench you created previously is not synthesiable on your FPGA. To test on actual hardware you need to create a hardware testbech by including IP that can stimulate the full adder's input and then use the ILA core to record the waveforms. The first step is to create a block diagram of our design.

  1. In Vivado, in the Flow Navigator, select Create block diagram under IP Integrator. The Create Block Design will open. Select OK.
  2. The BLOCK DESIGN tab will now open up. Under Sources, find Design Sources and then right click adder. Then select Add module to Block Diagram and this will add your full adder to the block diagram. Getting started AMD FPGA Hardware 01
  3. Now you need a clock source. Right click the block diagram and select Add IP then find the Clocking Wizard IP.
  4. A message on the block diagram stating Designer Assitance Available. Run Connection Automation should come up. Select Run Connection Automation. In the new Run Connection Automation window, select All Automation. Getting started AMD FPGA Hardware 02 This will automatically connect a sys_clock and a reset pin to the block diagram. Getting started AMD FPGA Hardware 03
  5. To write to your adder inputs, you will use a simple 3 bit counter. Right click the block diagram and select Add IP then find the Binary Counter IP.
  6. Double click the Binary Counter to open up the Re-customize IP window and modify the Output Width to be 3.
  7. Connect the CLK of the Binary Counter to clk_out1 of the clk_wiz_0.
  8. Add three Slice IP. Modify each one as follows:
    • xlslice_0 Din Width : 3, Din From: 0, Din Down To: 0, Dout Width: 0
    • xlslice_1 Din Width : 3, Din From: 1, Din Down To: 1, Dout Width: 0
    • xlslice_2 Din Width : 3, Din From: 2, Din Down To: 2, Dout Width: 0
  9. Connect the input of each Slice to the output of Binary Counter.
  10. Connect each Slice output as follows:
    • xlslice_0: Dout[0:0] -> A
    • xlslice_1: Dout[0:0] -> B
    • xlslice_2: Dout[0:0] -> Cin Getting started AMD FPGA Hardware 04
  11. Now you need to add the ILA. Right click the block diagram and select Add IP then find the ILA IP.
  12. Double click the ILA to customise it. Change Mount Type to Native and Number of Probes to 2.
  13. Attach the ILA input port clk to clk_out1 of the clk_wiz_0.
  14. Attach the ILA input port probe0[0:0] to S of the adder_0.
  15. Attach the ILA input port probe1[0:0] to COUT of the adder_0.
    Getting started AMD FPGA Hardware 05

Conclusion

You have stepped through how to set up a basic Test Driven Development flow for FPGAs. You used the simple example of a full adder which was broken into all of its gate level logic. Each module then had a test built before, you then made the code for it.

By placing these tests within different branches of the git repository, BeetleboxCI cant hen be used to trigger each test individually before running the final complete test.

What’s coming next?

In the next tutorial, you will be looking more in depth about the synthesis and simulation process. You will learn hwo to automate important steps, such as post-synthesis simulation.